No, the video is all generated internally to the FPGA. There's several PLLs on the FPGA itself, and I am using those to generate the various clocks. There's around 22 clock domains on the design as it stands. The problem is I would need some non-integer N/M ratio to get the right clock for the HDMI stuff from the 21.47Mhz domain. Right now video gets a clock that varies depending on video mode. i.e. it's 148.5Mhz in 1080p mode. There's no easy way to lock the two PLLs together (the one generating 21.47Mhz and the 148.5Mhz one) in the proper ratio to offer 60.09 hdmi.
The video always runs at 60.00 fps and it will cause cycle stealing on the snes side to make it stay in synch with the hdmi for the zero delay mode. If you run full/single buffered, the cycle stealing is turned off and is allowed to free run.
http://atariage.com/forums/topic/242970 … ?p=3966716
Es decir, no parece que haya intención de ofrecer opción para el refresco original del sistema, aunque tampoco hay impedimentos tecnológicos para que algún día ocurra. Quizás, cuando lancen el conversor a señal analógica (que, por cierto, se venderá aparte sin posibilidad de combinarlo en el envío), el planteamiento cambia.
